The present invention is directed to integrated circuits. More particularly, the invention provides dynamic threshold adjustment for over-current protection. Merely by way of example, the invention has been applied to a flyback power converter. But it would be recognized that the invention has a much broader range of applicability.
Generally, a conventional power conversion system often uses a transformer to isolate the input voltage on the primary side and the output voltage on the secondary side. To regulate the output voltage, certain components, such as TL431 and an opto-coupler, can be used to transmit a feedback signal from the secondary side to a controller chip on the primary side. Alternatively, the output voltage on the secondary side can be imaged to the primary side, so the output voltage is controlled by directly adjusting some parameters on the primary side.
FIG. 1 is a simplified diagram showing a conventional flyback power conversion system with primary-side sensing and regulation. The power conversion system 100 includes a primary winding 110, a secondary winding 112, an auxiliary winding 114, a power switch 120, a current sensing resistor 130, an equivalent resistor 140 for an output cable, resistors 150 and 152, and a rectifying diode 160. For example, the power switch 120 is a bipolar transistor. In another example, the power switch 120 is a MOS transistor.
To regulate the output voltage within a predetermined range, information related to the output voltage and the output loading often needs to be extracted. In the discontinuous conduction mode (DCM), such information can be extracted through the auxiliary winding 114. When the power switch 120 is turned on, the energy is stored in the secondary winding 112. Then, when the power switch 120 is turned off, the stored energy is released to the output terminal, and the voltage of the auxiliary winding 114 maps the output voltage on the secondary side as shown below.
                              V          FB                =                                                            R                2                                                              R                  1                                +                                  R                  2                                                      ×                          V              aux                                =                      k            ×            n            ×                          (                                                V                  o                                +                                  V                  F                                +                                                      I                    o                                    ×                                      R                    eq                                                              )                                                          (                  Equation          ⁢                                          ⁢          1                )            
where VFB represents a voltage at a node 154, and Vaux represents the voltage of the auxiliary winding 114. R1 and R2 represent the resistance values of the resistors 150 and 152 respectively. Additionally, n represents a turns ratio between the auxiliary winding 114 and the secondary winding 112. Specifically, n is equal to the number of turns of the auxiliary winding 114 divided by the number of turns of the secondary winding 112. Vo and Io represent the output voltage and the output current respectively. Moreover, VF represents the forward voltage of the rectifying diode 160, and Req represents the resistance value of the equivalent resistor 140. Also, k represents a feedback coefficient as shown below:
                    k        =                              R            2                                              R              1                        +                          R              2                                                          (                  Equation          ⁢                                          ⁢          2                )            
FIG. 2 is a simplified diagram showing a conventional operation mechanism for the flyback power conversion system 100. As shown in FIG. 2, the controller chip of the conversion system 100 uses a sample-and-hold mechanism. When the demagnetization process on the secondary side is almost completed and the current Isec of the secondary winding 112 almost becomes zero, the voltage Vaux of the auxiliary winding 112 is sampled at, for example, point A of FIG. 2. The sampled voltage value is usually held until the next voltage sampling is performed. Through a negative feedback loop, the sampled voltage value can become equal to a reference voltage Vref. Therefore,VFB=Vref  (Equation 3)
Combining Equations 1 and 3, the following can be obtained:
                              V          o                =                                            V              ref                                      k              ×              n                                -                      V            F                    -                                    I              o                        ×                          R              eq                                                          (                  Equation          ⁢                                          ⁢          4                )            
Based on Equation 4, the output voltage decreases with the increasing output current.
The primary-side sensing and regulation can be used for both pulse-width modulation (PWM) and the pulse-frequency modulation (PFM). FIGS. 3 and 4 are each a simplified diagram showing a conventional flyback power conversion system with primary-side sensing and regulation for constant output voltage under pulse-frequency modulation. As shown, the power conversion system 300 includes an exponential generator 310, a switch 320, a primary winding 340, a secondary winding 342, a capacitor 352, an error amplifier 360, a comparator 370, a demagnetization detector 380, an oscillator 390, and terminals 330, 332, and 334. Additionally, the power conversion system 300 also includes a resistor 322, a flip-flop component 374, a gate driver 384, and a comparator 386.
Similarly, the power conversion system 400 includes an exponential generator 410, a switch 420, a primary winding 440, a secondary winding 442, a capacitor 452, an error amplifier 460, a comparator 470, a demagnetization detector 480, an oscillator 490, and terminals 430, 432, and 434. Additionally, the power conversion system 400 also includes a resistor 422, a flip-flop component 474, a gate driver 484, and a comparator 486.
For example, the exponential generator 310 or 410 includes a switch-capacitor circuit controlled by an oscillation period T of an oscillator with a predetermined constant oscillation frequency. In another example, the switch 320 is a bipolar transistor, and the switch 420 is a MOS transistor.
As shown in FIG. 3 or 4, the demagnetization detector 380 or 480 outputs a signal 382 or 482 to the exponential generator 310 or 410 respectively. Additionally, the oscillator 390 or 490 also outputs a signal 392 or 492 to the exponential generator 310 or 410 respectively. Additionally, the switch 320 or 420 is controlled by a signal 396 or 496 through the terminal 334 or 434. Moreover, a signal 398 or 498 for sensing a current that flows through the primary winding 340 or 440 is generated by the resistor 322 or 422 respectively, and is received by the terminal 330 or 430 respectively.
FIG. 5 is a simplified diagram showing the conventional exponential generator 310 or 410 for the conventional power conversion system 300 or 400. The conventional exponential generator 500 can be used as the exponential generator 310 or the exponential generator 410. As shown, the exponential generator 500 includes switches 510, 520, and 540, capacitors 514 and 524, a counter 550, a frequency divider 560, a switch controller 570, and a NOT gate 580.
The switch 510 is controlled by a signal 512, the switch 520 is controlled by a signal 522, and the switch 540 is controlled by a signal 542. For example, the signal 542 is the signal 382 or 482. The signals 512 and 522 are generated based on at least a clock signal 532 outputted from an oscillator. For example, the clock signal 532 is the signal 392 or 492 generated by the oscillator 390 or 490 respectively.
Specifically, when the switch 510 is closed and the switches 520 and 540 are open, a reference voltage Vrefb charges the capacitor 514. In contrast, when the switch 520 is closed and the switches 510 and 540 are open, some charges are transferred from the capacitor 514 to the capacitor 524, causing the voltage on the capacitor 524 to rise. As the voltage on the capacitor 524 becomes higher and higher, the amount of additional charges transferred from the capacitor 514 to the capacitor 524 becomes less and less when, every time, the switch 510 is made open and the switch 520 is made closed, with the switch 540 remaining open.
Hence, if the switch 540 remains open, the voltage on the capacitor 524 rises approximately exponentially with the switch 510 alternating between being open and closed and the switch 520 alternating between being closed and open. When the switch 540 is closed by the signal 542, the capacitor 524 is discharged by a reference voltage Vrefa. Afterwards, the signal 542 changes the switch 540 from being closed to being open.
As shown in FIG. 5, the counter 550 also receives the signal 542 as well as a signal 552 from the frequency divider 560. The signal 552 represents rising edges of the clock signal 532 that is received by the frequency divider 560. The clock period of the clock signal 532 is denoted as T. When the signal 542 changes the switch 540 from being closed to being open, the counter 550 is also reset. Based on the signal 552, the counter 550 generates output signals 554. The output signals 554 include output signals clk2, clk4, . . . , clkm, . . . , and clkN, wherein 2≤m≤N. m and N are each equal to a power of 2 (e.g., 2 to the power of an integer). When the clkm signal rises from a logic low level to a logic high level (e.g., from the “0” level to the “1” level) for the first time since the reset, the time period since the last reset is
      n    ×    T    =                    m        ×        T            2        .  n represents the time period since the last reset in terms of the number of the clock periods.
Additionally, the counter 550 also sends an output signal 556 to a switch controller 570. Based on the output signal 556, the switch controller 570 closes only one of the switches that correspond to “clk”, “½ clk”, “¼ clk”, and “⅛ clk” respectively. Specifically, if 0≤n≤64, the switch corresponding to “clk” is closed, and the switching period for the switches 510 and 520 is equal to T. If 64<n≤128, the switch corresponding to “½ clk” is closed, and the switching period for the switches 510 and 520 is equal to 2T. If 128<n≤512, the switch corresponding to “¼ clk” is closed, and the switching period for the switches 510 and 520 is equal to 4T. If n>512, the switch corresponding to “⅛ clk” is closed, and the switching period for the switches 510 and 520 is equal to 8T. Hence,
                                          V            ramp                    ⁡                      (            n            )                          =                                            (                                                V                  refb                                -                                  V                  refa                                            )                        ×                          (                              1                -                                  e                                      -                                          (                                                                        n                          ×                          T                                                τ                                            )                                                                                  )                                +                      V            refa                                              (                  Equation          ⁢                                          ⁢          5                )            
where Vramp represents the voltage magnitude of a signal 526. For example, the signal 526 is the signal 312 or 412. Additionally, Vrefa and Vrefb each represent a constant voltage level. For example, Vrefa equals 1V, and Vrefb equals 3V. Moreover, n represents the time for the signal 526 to rise since the last reset of the counter 550 in terms of the number of the clock periods. T is the clock period of the clock signal 532. Furthermore, τ is the time constant. Specifically, if 0≤n≤64, τ=128×T; if 64<n≤128, τ=256×T; if 128<n≤256, τ=512×T; and if 256<n, τ=1024×T.
Returning to FIG. 3 or 4, when the switch 320 or 420 is turned on, the transformer stores energy. The current flowing through the primary winding 340 or 440 ramps up linearly, and the signal 398 or 498 (e.g., a current-sensing voltage) also ramps up linearly. The signal 398 or 498 is received by the comparator 386 or 486 respectively, and is compared with a threshold signal 399 or 499 for over-current protection (OCP) respectively. For example, the threshold signal 399 or 499 is a threshold voltage that is equal to 0.5 V. In response, the comparator 386 or 486 outputs a comparison signal 388 or 499 to the flip-flop component 374. For example, if the signal 398 exceeds the threshold signal 399 in magnitude, the comparison signal 388 is at the logic high level. In another example, if the signal 498 exceeds the threshold signal 499 in magnitude, the comparison signal 488 is at the logic high level.
When the switch 320 or 420 is turned off, the energy stored in the transformer is released to the output terminal. The demagnetization process starts, and the current flowing through the secondary winding 342 or 442 ramps down linearly. When the demagnetization process almost ends and the current flowing through the secondary winding 342 or 442 approaches zero, a sampling signal 350 or 450 is generated to sample the feedback voltage at the terminal 332 or 432. The sampled voltage is held on the capacitor 352 or 452. Additionally, the sampled/held voltage is compared with a reference voltage Vref, such as 2V, and the difference between the sampled/held voltage and the reference voltage Vref is amplified by the error amplifier 360 or 460 to generate an amplified signal 362 or 462. The amplified signal 362 or 462 is received by the negative input terminal of the comparator 370 or 470, whose output signal 372 or 472 is received by the flip-flop component 374 or 474 and used to generate the signal 396 or 496 respectively.
The flip-flop component 374 receives the signals 372 and 388, and in response generates a signal 376. If the signal 372 is at the logic high level and the signal 388 is at the logic low level, the signal 376 is at the logic high level. In contrast, if the signal 372 is at the logic high level and the signal 388 is also at the logic high level, the signal 376 is at the logic low level. Similarly, the flip-flop component 474 receives the signals 472 and 488, and in response generates a signal 476. If the signal 472 is at the logic high level and the signal 488 is at the logic low level, the signal 476 is at the logic high level. In contrast, if the signal 472 is at the logic high level and the signal 488 is also at the logic high level, the signal 476 is at the logic low level.
As shown in FIG. 3, the signal 376 is received by the gate driver 384, which outputs the signal 396 to the switch 320. If the signal 376 is at the logic high level, the signal 396 is also at the logic high level and causes the switch 320 to be turned on. In contrast, if the signal 376 is at the logic low level, the signal 396 is also at the logic low level and causes the switch 320 to be turned off. Similarly, as shown in FIG. 4, the signal 476 is received by the gate driver 484, which outputs the signal 496 to the switch 420. If the signal 476 is at the logic high level, the signal 496 is also at the logic high level and causes the switch 420 to be turned on. In contrast, if the signal 476 is at the logic low level, the signal 496 is also at the logic low level and causes the switch 420 to be turned off.
Additionally, when the demagnetization process starts, a ramp signal 312 or 412 of the exponential generator 310 or 410 is restored to an initial value. For example, the ramp signal 312 or 412 is the signal 526, which is restored to Vrefa according to Equation 5 when the demagnetization process starts. After the demagnetization process is completed, the ramp signal 312 or 412 increases exponentially. If the ramp signal 312 or 412 becomes higher than the amplified signal 362 or 462 in magnitude, the comparison signal 372 or 472 is at the logic high level (e.g., at the “1” level), and the switch 320 or 420 is turned on.
Referring to FIG. 3 or 4, the larger the output load of the power conversion system 300 or 400 is, the lower the amplified signal 362 or 462 of the error amplifier 360 or 460 becomes in magnitude. Hence, the time period when the switch 320 or 420 remains turned off also becomes shorter. In contrast, the smaller the output load of the power conversion system 300 or 400 is, the higher the amplified signal 362 or 462 of the error amplifier 360 or 460 becomes in magnitude. Hence, the time period when the switch 320 or 420 remains turned off also becomes longer.
FIG. 6 is a simplified diagram showing certain conventional waveforms for the power conversion system 300 or 400. A waveform 610 represents the signal 382 or 482 as a function of time, a waveform 620 represents the signal 396 or 496 as a function of time, a waveform 630 represents the signal 398 or 498 as a function of time, a waveform 640 represents the signal 312 or 412 as a function of time, a waveform 650 represents the signal 362 or 462 as a function of time. As shown in FIG. 6, the time period toff when the switch 320 or 420 remains turned off is equal to tDemag+tramp. tDemag represents the time period of the demagnetization process, and tramp represents the time period for the signal 312 or 412 to rise to the level of the signal 362 or 462 in magnitude. For example, the signal 312 or 412 is the signal 526 generated by the exponential generator 500. The voltage magnitude Vramp of the signal 526 rises until the switch 540 is closed by the signal 542. In another example, tramp is equal to nramp×T. In yet another example, at n=nramp, Vramp is smaller than Vrefb according to Equation 5, where n represents the time for the signal 526 to rise in terms of the number of the clock periods. In yet another example, n×T is represented by the output signals 554.
But the power conversion system 300 or 400 often cannot provide effective dynamic response with load changes. Hence it is highly desirable to improve the techniques of dynamic response using primary-side sensing and regulation.